As circuit technology evolves, transistors shrink, whether in length, width, or thickness. Transistor shrinkage may cause one or more effects that negatively affect operation of the circuit. A phenomenon, known as negative bias temperature instability (NBTI), is one source of transistor failure. NBTI occurs in p-type metal oxide semiconductor (PMOS) transistors whenever the voltage at the gate is negative (logic input “0”). NBTI causes degradation of the transistor, which shortens its usable life.
Like other transistor-based circuits, memory cells are adversely affected by the NBTI phenomenon. Although variations exist, typical memory cells consist of two inverters, arranged such that the output of a first inverter is coupled to the input of a second inverter, and vice-versa. With such a configuration, one of the inverters has a negative voltage (logic input “0”) at its input at all times, resulting in NBTI degradation. The best-case degradation occurs when the value of each inverter is “0” 50% of the time, meaning that both PMOS transistors degrade at the same rate. Because of the configuration of the memory cells, achieving a degradation rate below 50% is unfeasible.
Thus, there is a continuing need to address the NBTI-related issues associated with memory cells.